1. Field of the Invention
The invention relates to an ESD protection circuit and a semiconductor device.
2. Related Art
A field effect transistor (hereinafter, “FET”) in a semiconductor integrated circuit is scaled to follow the improved performance of the FET. In recent years, it is by no means unusual to reduce a thickness of a gate insulating film, converted into silicon dioxide, of the FET to about 1 nm.
If the thickness of the gate insulating film is smaller, withstand voltage against electrically dielectric breakdown greatly drops to depend on the thickness of the gate insulating film. In case of a semiconductor device including an FET that includes such a thin gate insulating film, if static electricity emanating from a machine or a human during manufacturing or during use is discharged into the semiconductor device, a high voltage is applied to the gate insulating film, often resulting in breakdown of the gate insulating film. Such a phenomenon is referred to as “ESD (Electrostatic Discharge) breakdown”.
To prevent entry of surge current from outside, therefore, many semiconductor devices are designed to include ESD protection circuits to prevent ESD breakdown from occurring to gate insulating films (see for example, Japanese Patent Application Laid-open No. H11-17117 (hereinafter, “Patent Document 1”)).
An ESD protection circuit disclosed in Patent Document 1 is configured as follows. An inverter interposes between an external GND terminal and a drain of an internal circuit to prevent the drain of the internal circuit from being directly connected to the external GND terminal. By so configuring, even if an input to a transfer gate of the internal circuit is to be set to GND level, current is prevented from flowing from a drain of a P-type transistor to VDD via a well and electrons are prevented from flowing from a drain of an N-type transistor to an external power supply potential VDD terminal.
However, the ESD protection circuit disclosed in the Patent Document 1 has the following problems. If surge is as fast as a CDM (Charged Device Model) that is one standard of the ESD, voltage overshoot occurs in an initial stage in which a protection element responds to the surge, resulting in the breakdown of the gate insulating film of the internal circuit.
The ESD breakdown resulting from the CDM is conspicuous particularly to a small-sized power supply circuit having a small-sized separate power supply.